Grade 8 Cello - Distinction

Jasper Formal Fundamentals v2212 Exam

Grade 4 Piano - Merit

Cadence Student Ambassador Exam

Bronze Award

SystemVerilog Assertions v5.1 Exam

Silver Award

Timing Closure for Intel® FPGAs Course Completion

Jasper Sequential Equivalence Checking App v21.06 RAKS Exam

UKESF Scholar

Assistant Librarian

Lead Secretary

Care Home Assistant

We deliver over 600 free hot meals a week across Cambridge, with no criteria to be a recipient whatsoever

Cook, Cleaner, and Delivery Driver

Farm Hand

Lead Content Manager

Community Volunteer

Common Entrance

Master of Engineering (MEng)

A-level

GCSE

• Researched designs for nuclear plants, sourcing information from reliable online resources and experienced employees.
• Formulated presentations to compare the efficacy of various types of power plants and provided information on each's highlights and drawbacks.
• Presented these topics before large groups of employees, receiving encouraging and useful feedback on my presentational skills.

Research And Development Engineer

• Proved cache prefetch functionality in 5G RISC-V CPU models with embedded C and testbenches written in CocoTB.
• Optimised CPU performance through benchmarks such as Dhrystone and migrating cell library technologies.
• Innovated a validation system for continuous regression workflows in Python, streamlining development processes.

5G RISC-V CPU RTL Design Engineer

• Worked on updating the company’s website, focusing on visual design and user experience.
• Analysed and compared close competitors’ websites; organised and presented proposals for improvements that were subsequently taken on.
• Carried door-to-door recruitment, encouraging doctors to sign up for Findoc’s service.

Web Developer

Solutions RTL Design Engineer

I worked with the Solutions Engineering Front End (SOFE) team to develop cutting-edge and industry-leading automation tools for design and development

Graduate Solutions RTL Design Engineer

• Joined the Snapdragon X CPU team to enhance core components, leveraging formal tools to maintain high standards.
• Gained broad experience in Arm CPU design, including hands-on work with SystemVerilog, TCL, and Cadence tools.
• Confirmed sequential equivalence of clock gating in the MMU block, contributing to increased power efficiency.

Snapdragon X CPU RTL Design Engineer

Just some guy

youtube

github

Know about Erwan Régy's work experience, education, bootcamps, certifications, and much more. Erwan Régy

Resume of Erwan Régy • Peerlist

SystemVerilog

Canva

Python