Designed a complete RTL-to-gates self-balancing Segway controller in SystemVerilog: PID pitch balance control, differential PWM motor drive, A2D interface, SPI inertial sensor interface, UART command receiver, and a steering enable FSM. Synthesized to a gate-level netlist at a 333 MHz target clock using Synopsys Design Compiler on the SAED32 32nm library; verified with 10+ ModelSim testbenches covering balance response, steering, and overcurrent safety cutoff.