• Collaborated within a multidisciplinary team to design and integrate Kyber post-quantum cryptographic hardware into a secure telemetry system. • Designed modular arithmetic hardware (mod 3329) to support post-quantum cryptographic operations used in the Kyber algorithm. • Implemented Barrett reduction and Montgomery multiplication architectures to improve computational efficiency and hardware performance. • Developed self-checking Verilog testbenches with randomized inputs to verify functional correctness and improve validation coverage. • Analyzed latency, resource utilization, and critical path timing to support performance optimization and design refinement.