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• Implemented an FSM-based control architecture (CONTROLBLOCK) for reliable hardware synchronization through modular VHDL coding and block designing using Xilinx Vivado on Zynq-7000 FPGA.
• Collaborated with cross-functional teams on SEM, utilizing Agile methodologies for iterative development.
• Developed scalable Python backend services for real-time hardware data processing, ensuring sub-100ms response latency. Created RESTful APIs to connect FPGA hardware with a React.js frontend, enhancing system efficiency.

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AI & ML enthusiast with experience in software development, computer vision, and embedded systems.

Know about Tejaswini Kapure's work experience, education, bootcamps, certifications, and much more. Tejaswini Kapure

Resume of Tejaswini Kapure • Peerlist