Over 6 years of experience in safety-critical systems testing, flight health monitoring, and technical operations.

Vishakha Hanumante  • Peerlist

In the proposed research paper, we are analyzing the conventional Carbon nanotube Field- effect transistor (CNTFET) and its following drawbacks such as high on current, low on-off switching ration, etc.  a modified Schottky barrier carbon nanotube field-effect transistor (SB-CNTFET)  developed by adjusting its doping concentration of Drain. These newly developed SB-CNTFET structures have benefits of both Schottky barrier and ohmic contact of the lightly doped drain. In the proposed research report, the conclusion drawn from the resource paper shows significant depletion in leakage current as well increment in the on-off current ratio as well as cut-off frequency. The LDD-CNTFET shows commentable immunity boost against the short-channel device effect, which is demonstrated by different analytical experiments.

Modified Schottky Barrier CNTFET with lightly

•	Devised breath analyzer sensor using Raspberry-pi •	Developed python scripts for detection of alcohol concentration

Automated drunk & drive disabling (

•	Designed and implemented layout simulation of a 5-stage, 32-bit RISC processor in VHDL •	Implemented behavioral study of each instruction logic through bottom up approach •	Developed source code realization for the memory operation with timing analysis through testbench generation using ModelSim. that improved total path delay of 21.25 sec with memory usage of 108580 kb

Design 5-stage pipeline RISC Processor

•	Implemented Serial Port device driver in a Linux environment to establish peripheral communication of Computer •	Developed shell scripts to invoke transmission thread and design module written in C •	Tested driver’s routing capability using Loop Back mode and data transfer between two PCs using RS232

Communication between two PCs using Serial Po

•	Designed and implemented AES encryption and decryption algorithm on 128-bit input data bits using MATLAB

AES Encryption Algorithm

•	Designed 45nm technology MOSFET with emphasis on power optimization •	Analyzed power optimization by comparing Spice decks of CMOS, GRFET and FINFET with HSPICE simulation

Low power design and optimization technique

•	Designed a FIFO Memory of 8-bit data width consist of 16 stages. The memory operations were defined using Status Signals •	A Verilog Testbench was architecture to check the functional behavior of the design.

Design and implementation of FIFO Memory usin

•	Designed serial port communication between two ports using Dual high-speed Differential Linear driver •	Developed data transmission feature and GUI interface using Embedded C and Microsoft Visual Basic 6.0